1. Field of the Invention
The invention relates to the field of memories, particularly the accessing of dynamic, random-access memories by central processing units.
2. Prior Art
Many computer systems, particularly microcomputers, employ dynamic, random-access memories which are accessed directly by central processing units (CPU). These memories require periodic refresh cycles and often these cycles are asynchronous with CPU operation. Consequently, a collision can occur between a memory access cycle such as a read cycle and a refresh cycle. Most often, the read cycle is aborted in favor of the refresh cycle, since otherwise the data in the memory might be lost. Obviously, when this occurs the operation of the CPU is slowed. A memory provided "not ready" signal is used in some cases to indicate a collision and then to inactivate clock cycles associated with CPU operations. To make use of this time, often these cycles are used for internal CPU housekeeping.
Most often, these memories provide a data valid signal or the equivalent (e.g., acknowledge) to indicate that data has been accessed and is on the computer bus. This signal which may occur asynchronously with the computer operation is converted to a ready signal which is synchronized with the computer operation. The CPU then acts on the ready signal to sense the data on the bus or to write data onto the bus. In some cases an advanced data valid signal (referred to as advanced acknowledge) is provided by the memory to indicate that accessing will occur without collision with a refresh cycle. The absence of this pulse, by way of example, can be used to allow the CPU to do other functions while waiting for the refresh cycle to be completed and for data to be accessed.
The typical protocol for accessing a memory in a microcomputer results in a time gap between the time when the memory couples data to the bus and when the CPU senses the data even when collision occurs. One full clock cycle is lost with this protocol and this can result in a loss of up to 40% of the CPU's time. This will be explained in more detail in conjunction with FIG. 2.
As will be seen, the present invention reduces the accessing time for those cycles where collision does not occur.